HAL1 CRYP –> HAL2 AES ¶
The goal of this page is to show how to migrate the initialization sequence using STM32CubeMX2:
Open STM32CubeMX2 AES configuration panel.
Configure the SW layer HAL.
Configure the main AES features.
Configure the advanced AES features if needed.
Configure the AES DMA(s) if the application requires the AES to be used in DMA mode.
Configure the NVIC if the application requires the AES to be used in IT mode.
Generate the code.
HAL AES configuration panel ¶
Create a new project with the STM32CubeMX2, then start the initialization and the main configuration.
HAL AES main features configuration ¶
Configure the AES main features.
HAL AES advanced features configuration ¶
Configure the advanced AES features if needed.
DMA configuration ¶
Configure the AES DMA channels if the application requires to use the AES in DMA mode.
NVIC configuration ¶
Configure the NVIC in case of an interrupt.
Generated AES initialization and de-initialization sequences ¶
The AES initialization and de-initialization sequences are generated in the
mx_aes_init
and
mx_aes_deinit
functions in the
mx_aes.c
file under
$YOUR_PROJECT_NAME$/$YOUR_PROJECT_NAME$_SW/generated/STM32Cube_CodeGen.
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Topic |
HAL1 Code Snippet |
HAL2 Code Snippet |
|---|---|---|
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Handle declaration |
CRYP_HandleTypeDef hcryp;
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static hal_aes_handle_t hAES;
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Initialization and configuration sequence |
void MX_AES_Init(void)
{
hcryp.Instance = AES;
hcryp.Init.DataType = CRYP_NO_SWAP;
hcryp.Init.KeySize = CRYP_KEYSIZE_128B;
hcryp.Init.pKey = (uint32_t *)pKeyAES;
hcryp.Init.pInitVect = (uint32_t *)pInitVectAES;
hcryp.Init.Algorithm = CRYP_AES_GCM_GMAC;
hcryp.Init.Header = (uint32_t *)HeaderAES;
hcryp.Init.HeaderSize = 1;
hcryp.Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_WORD;
hcryp.Init.HeaderWidthUnit = CRYP_HEADERWIDTHUNIT_WORD;
hcryp.Init.KeyIVConfigSkip = CRYP_KEYIVCONFIG_ALWAYS;
hcryp.Init.KeyMode = CRYP_KEYMODE_NORMAL;
if (HAL_CRYP_Init(&hcryp) != HAL_OK)
{
Error_Handler();
}
}
void HAL_CRYP_MspInit(CRYP_HandleTypeDef* crypHandle)
{
if(crypHandle->Instance==AES)
{
__HAL_RCC_AES_CLK_ENABLE();
HAL_NVIC_SetPriority(AES_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(AES_IRQn);
}
}
void MX_LPDMA1_Init(void)
{
__HAL_RCC_LPDMA1_CLK_ENABLE();
handle_LPDMA1_Channel0.Instance = LPDMA1_Channel0;
handle_LPDMA1_Channel0.Init.Request = DMA_PERIPH_TO_MEMORY;
handle_LPDMA1_Channel0.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
handle_LPDMA1_Channel0.Init.Direction = DMA_MEMORY_TO_MEMORY;
handle_LPDMA1_Channel0.Init.SrcInc = DMA_SINC_FIXED;
handle_LPDMA1_Channel0.Init.DestInc = DMA_DINC_FIXED;
handle_LPDMA1_Channel0.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
handle_LPDMA1_Channel0.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
handle_LPDMA1_Channel0.Init.Priority = DMA_LOW_PRIORITY_LOW_WEIGHT;
handle_LPDMA1_Channel0.Init.SrcBurstLength = 1;
handle_LPDMA1_Channel0.Init.DestBurstLength = 1;
handle_LPDMA1_Channel0.Init.TransferAllocatedPort =
DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT0;
handle_LPDMA1_Channel0.Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
handle_LPDMA1_Channel0.Init.Mode = DMA_NORMAL;
if (HAL_DMA_Init(&handle_LPDMA1_Channel0) != HAL_OK)
{
Error_Handler();
}
if (HAL_DMA_ConfigChannelAttributes(&handle_LPDMA1_Channel0,
DMA_CHANNEL_NPRIV) != HAL_OK)
{
Error_Handler();
}
}
void MX_LPDMA2_Init(void)
{
__HAL_RCC_LPDMA2_CLK_ENABLE();
handle_LPDMA2_Channel0.Instance = LPDMA2_Channel0;
handle_LPDMA2_Channel0.Init.Request = DMA_MEMORY_TO_PERIPH;
handle_LPDMA2_Channel0.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
handle_LPDMA2_Channel0.Init.Direction = DMA_MEMORY_TO_MEMORY;
handle_LPDMA2_Channel0.Init.SrcInc = DMA_SINC_FIXED;
handle_LPDMA2_Channel0.Init.DestInc = DMA_DINC_FIXED;
handle_LPDMA2_Channel0.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
handle_LPDMA2_Channel0.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
handle_LPDMA2_Channel0.Init.Priority = DMA_LOW_PRIORITY_LOW_WEIGHT;
handle_LPDMA2_Channel0.Init.SrcBurstLength = 1;
handle_LPDMA2_Channel0.Init.DestBurstLength = 1;
handle_LPDMA2_Channel0.Init.TransferAllocatedPort =
DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT0;
handle_LPDMA2_Channel0.Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
handle_LPDMA2_Channel0.Init.Mode = DMA_NORMAL;
if (HAL_DMA_Init(&handle_LPDMA2_Channel0) != HAL_OK)
{
Error_Handler();
}
if (HAL_DMA_ConfigChannelAttributes(&handle_LPDMA2_Channel0,
DMA_CHANNEL_NPRIV) != HAL_OK)
{
Error_Handler();
}
}
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hal_aes_handle_t *mx_aes_init(void)
{
if (HAL_AES_Init(&hAES, HAL_AES) != HAL_OK)
{
return NULL;
}
HAL_RCC_AES_EnableClock();
HAL_AES_ECB_SetConfig(&hAES);
HAL_AES_SetDataSwapping(&hAES, HAL_AES_DATA_SWAPPING_NO);
/* Configure the DMA OUT */
HAL_RCC_LPDMA1_EnableClock();
if (HAL_DMA_Init(&hLPDMA1_CH1, HAL_LPDMA1_CH1) != HAL_OK)
{
return NULL;
}
hal_dma_direct_xfer_config_t xfer_cfg_aes_out_dma;
xfer_cfg_aes_out_dma.request = HAL_LPDMA1_REQUEST_AES_OUT;
xfer_cfg_aes_out_dma.direction = HAL_DMA_DIRECTION_PERIPH_TO_MEMORY;
xfer_cfg_aes_out_dma.src_inc = HAL_DMA_SRC_ADDR_FIXED;
xfer_cfg_aes_out_dma.dest_inc = HAL_DMA_DEST_ADDR_INCREMENTED;
xfer_cfg_aes_out_dma.src_data_width = HAL_DMA_SRC_DATA_WIDTH_WORD;
xfer_cfg_aes_out_dma.dest_data_width = HAL_DMA_DEST_DATA_WIDTH_WORD;
xfer_cfg_aes_out_dma.priority = HAL_DMA_PRIORITY_LOW_WEIGHT_LOW;
if (HAL_DMA_SetConfigPeriphDirectXfer(&hLPDMA1_CH1, &xfer_cfg_aes_out_dma) != HAL_OK)
{
return NULL;
}
/* Enable the interruption for LPDMA1_CH1 */
HAL_CORTEX_NVIC_SetPriority(LPDMA1_CH1_IRQn, HAL_CORTEX_NVIC_PREEMP_PRIORITY_0, HAL_CORTEX_NVIC_SUB_PRIORITY_0);
HAL_CORTEX_NVIC_EnableIRQ(LPDMA1_CH1_IRQn);
/* Link the Output DMA handle to the AES handle */
if (HAL_AES_SetOutDMA(&hAES, &hLPDMA1_CH1) != HAL_OK)
{
return NULL;
}
/* Configure the DMA IN */
HAL_RCC_LPDMA1_EnableClock();
if (HAL_DMA_Init(&hLPDMA1_CH0, HAL_LPDMA1_CH0) != HAL_OK)
{
return NULL;
}
hal_dma_direct_xfer_config_t xfer_cfg_aes_in_dma;
xfer_cfg_aes_in_dma.request = HAL_LPDMA1_REQUEST_AES_IN;
xfer_cfg_aes_in_dma.direction = HAL_DMA_DIRECTION_MEMORY_TO_PERIPH;
xfer_cfg_aes_in_dma.src_inc = HAL_DMA_SRC_ADDR_INCREMENTED;
xfer_cfg_aes_in_dma.dest_inc = HAL_DMA_DEST_ADDR_FIXED;
xfer_cfg_aes_in_dma.src_data_width = HAL_DMA_SRC_DATA_WIDTH_WORD;
xfer_cfg_aes_in_dma.dest_data_width = HAL_DMA_DEST_DATA_WIDTH_WORD;
xfer_cfg_aes_in_dma.priority = HAL_DMA_PRIORITY_LOW_WEIGHT_LOW;
if (HAL_DMA_SetConfigPeriphDirectXfer(&hLPDMA1_CH0, &xfer_cfg_aes_in_dma) != HAL_OK)
{
return NULL;
}
/* Enable the interruption for LPDMA1_CH0 */
HAL_CORTEX_NVIC_SetPriority(LPDMA1_CH0_IRQn, HAL_CORTEX_NVIC_PREEMP_PRIORITY_0, HAL_CORTEX_NVIC_SUB_PRIORITY_0);
HAL_CORTEX_NVIC_EnableIRQ(LPDMA1_CH0_IRQn);
/* Link the Input DMA handle to the AES handle */
if (HAL_AES_SetInDMA(&hAES, &hLPDMA1_CH0) != HAL_OK)
{
return NULL;
}
/* Enable the interruption for AES */
HAL_CORTEX_NVIC_SetPriority(AES_IRQn, HAL_CORTEX_NVIC_PREEMP_PRIORITY_0, HAL_CORTEX_NVIC_SUB_PRIORITY_0);
HAL_CORTEX_NVIC_EnableIRQ(AES_IRQn);
return &hAES;
}
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|
Deinitialization sequence |
void MX_AES_DeInit(void)
{
if (HAL_CRYP_DeInit(&hcryp) != HAL_OK)
{
Error_Handler();
}
}
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef* crypHandle)
{
if(crypHandle->Instance==AES)
{
__HAL_RCC_AES_CLK_DISABLE();
HAL_NVIC_DisableIRQ(AES_IRQn);
}
}
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void mx_aes_deinit(void)
{
/* Disable the interruption for AES */
HAL_CORTEX_NVIC_DisableIRQ(AES_IRQn);
(void)HAL_AES_DeInit(&hAES);
HAL_RCC_AES_Reset();
HAL_RCC_AES_DisableClock();
/* De-initialize the DMA channel */
HAL_DMA_DeInit(&hLPDMA1_CH0);
/* Disable the interruption for DMA */
HAL_CORTEX_NVIC_DisableIRQ(LPDMA1_CH0_IRQn);
/* De-initialize the DMA channel */
HAL_DMA_DeInit(&hLPDMA1_CH1);
/* Disable the interruption for DMA */
HAL_CORTEX_NVIC_DisableIRQ(LPDMA1_CH1_IRQn);
}
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IRQ handle function |
void AES_IRQHandler(void)
{
HAL_AES_IRQHandler(&hcryp);
}
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void AES_IRQHandler(void)
{
HAL_AES_IRQHandler(&hAES);
}
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